Linaro Connect Bangkok

Machine Learning and Big Data applications are fundamentally changing the way that the processing of data happens. Classic processor data flows are now being augmented with off-chip accelerators that can be customized for specific types of applications from compute accelerators to network traffic acceleration. This has driven an industry wide movement towards accelerators and heterogeneous compute. For many of today’s compute tasks, accelerators can complete the needed functionality both faster and with lower power consumption than the processor working on its own. However, unmanaged heterogeneity can bring software complexity.
Cache Coherent Interconnect for Accelerators or CCIX™ (pronounced ‘see 6’) is a high-performance, chip-to-chip interconnect architecture that provides a cache coherent framework for heterogeneous system architectures. CCIX is designed with an aim to simplify heterogeneous system architecture while simultaneously improving performance – factors that are vital to design, optimization and deployment of accelerator based systems.

In this talk, we provide an introduction to CCIX from a software point of view. We will first introduce key CCIX features and capabilities, and how they benefit heterogeneous system design. We next illustrate why a CCIX system is fundamentally viewed as a NUMA system with heterogeneous properties. We will then provide a detailed introduction to individual components of the CCIX software stack – the CCIX boot firmware, UEFI and ACPI requirements, the CCIX programming model, hardware/software interfaces, OS and Management software architectures, Power Management and RAS.

We wrap up with a broad overview of ongoing efforts to enable CCIX in the existing ecosystems, and challenges thereof. We then solicit the audience’s suggestions on how these can be overcome in order to bring CCIX to full fruition in the Arm ecosystem.